Prior art bus structures comprise inputs for three signals which are used for the transmission of serial data, the bus having in addition to the data (DATA) and clock (CLK) lines a signal (SLE) indicating the end of data transmission. During the transmission the rising or falling edge of the clock line (CLK) clocks the data (DATA).
After the last bit the state of the SLE line is changed for a moment. The last bits of the data are an address indicating to which register the data shall be transmitted. Because the address bits are the last bits, the data must be first clocked into all registers, and the SLE triggers the data into the addressed register. The clock line must be connected to all registers at different locations of the integrated circuit (IC), whereby the line will be long and will easily cream cross-talk.
Cross-talk is the coupling of a (digital) signal into another signal, to the supply voltage or to the earth level. It is particularly inconvenient in phase locked loop (PLL) frequency synthesis, because the cross-talk appears as interference in the spectrum of the Voltage Controlled Oscillator (VCO), and thus also as a spurious response in the transmission branch (Tx).
Previously the cross-talk was not particularly inconvenient, as the PLL IC had only 2 to 3 registers, and it was possible to locate them so that there was a minimum of cross-talk. Moreover, in analog mobile phone systems it was possible to have a stronger filtering of the VCO control voltage, which experienced cross-talk from the data transmission clock signal, than in digital systems (there is a longer channel switch-over period, which depends on the bandwidth of the filter). When the degree of integration increases the circuits will be larger, the number of registers in one IC will increase and they can no longer be located so as to have sufficiently low cross-talk.
The prior art bus solution requires three signals and thus also three pins of the microcircuit. The size of the housing could be reduced and also the area of the microcircuit would be reduced (in a pad restricted circuit), if the number of the circuit's Input/Output (I/O) signals could be reduced.
European patent application EP 0 390 978 presents a prior art solution. In this patent application data can be transmitted in both directions. However, the solution utilizes a data format with a packet structure, which substantially limits the use of the invention. The invention also uses pulse width modulation with only two levels.